1. Technical Field
This invention pertains to CMOS integrated circuit processing, and, more particularly, to radiation hardening of shallow trench isolation (“STI”) or local oxidation (“LOCOS”) of a silicon field oxide region of an integrated circuit device, to prevent formation of leakage paths either within a device or to adjacent devices in high radiation environments.
2. Background Art
The field of radiation hardening in semiconductor devices deals in part with the problem of electron-hole pairs generated by the passage of ionizing radiation through the semiconductor devices. Electron-hole pairs generated in bulk silicon do not present a severe problem, because the electrons and holes recombine rapidly. Electron-hole pairs formed in silicon dioxide, however, are more difficult to deal with because the electrons are far more mobile than the holes and may become separated from the holes. This makes recombination more difficult and results in an accumulation of net positive charge in the silicon dioxide, or other dielectric film.
The conventional process for laterally isolating semiconductor circuits uses a field oxide between the active regions. One method of producing this field oxide is the shallow trench isolation or “STI” process. The STI process produces a recessed thick oxide layer separating adjacent semiconductor devices. This thick oxide layer is extremely susceptible to trapping positive charge in an ionizing radiation environment. This effect is cumulative and eventually results in lowering of the threshold voltage of the parasitic field oxide transistors occurring between adjacent transistors, such that these adjacent transistors are no longer isolated from one another.
N-channel transistors, formed in a P-well and separated by field oxide, are particularly affected by this phenomenon. The trapped positive charge in the field oxide repels positively charged carriers (holes) and attracts negatively charged carriers (electrons) in the surface of the underlying silicon layer. This accumulation of negatively charged carriers in the P-well adjacent to the field oxide causes inversion of the P-type silicon and creates a conductive channel or leakage path between N-doped drain and source regions of adjacent N-channel transistors. The accumulated negative charge in the P-well region can also create a leakage path from the source to drain of a single N-channel transistor, thus shorting out the N-channel transistor. But perhaps the most severe leakage path occurs between a P-well active region adjacent to an N-well active region, especially where polysilicon is used as an interconnect between both active regions. Thus, these undesirable parasitic transistors dominate circuit behavior and the circuit can no longer function as designed.
Conventionally, in the LOCOS process or variations thereof, the area that will be the field oxide region is implanted before growth of the field oxide with an ion dose that is calculated to suppress the operation of parasitic transistors under normal (no ionizing radiation) environments and operating conditions. The field oxide is conventionally grown by a wet thermal process. With the field implant process, there is a dopant gradient extending down into the substrate, with a high concentration at the surface changing to a background bulk concentration at some depth below the surface. The nature of the bulk silicon underlying the semiconductor circuit depends on the nature of the process used to fabricate the circuit, such as NMOS, PMOS, or CMOS processes. While this conventional method offers some protection against parasitic leakage paths under normal operating conditions, it is not possible to obtain the doping concentrations necessary to produce radiation hardened devices with acceptable performance for radiation doses greater than about 10 to 20 krad(Si).
Conventionally, in the STI process or variations thereof, the area that will be the field oxide region is etched out from the bulk silicon before deposition of the field oxide. A thin buffer oxide is conventionally grown by wet or dry processes to passivate the etched silicon surface and to reduce stress at the trench corners. There is no separate field oxide implant intended to suppress the operation of parasitic leakage paths under normal environmental and operating conditions. Multiple high energy implants are used to define the wells and threshold voltages of the transistors resident therein. While some measure of protection against parasitic leakage paths is achievable, it is still not possible to obtain the doping concentrations necessary to produce radiation hardened devices with acceptable performance for radiation doses greater than about 50 krad(Si).
Referring generally now to FIGS. 1-6, a conventional STI semiconductor process is shown in a series of cross-sectional drawing figures. In FIG. 1, a silicon substrate 10 is oxidized to form a thin silicon dioxide layer 12. A thicker Si3N4 layer 14 is formed on the surface of the silicon dioxide layer 12. In FIG. 2, trenches 16 are formed in each of layers 10, 12, and 14. In FIG. 3, a thick layer 18 of SiO2 including thin thermal grown sides and bottom portions is conformally deposited over the surface of the integrated circuit, such that the trenches are completely filled with SiO2. In FIG. 4, the thick layer 18 of SiO2 is planarized to the surface of the oxide layer 12. In FIG. 5, a patterned photoresist layer 20 is formed, with an etched portion for forming an N-well in substrate 10. Multiple implants 22 are delivered to the substrate 10, such as phosphorous or arsenic implants as is known in the art. In FIG. 6, the N-well 28 is formed. Another patterned photoresist layer 24 is formed to allow implanting of a P-well through multiple implants 26.
In FIG. 6, dotted lines 30 and 32 are depth and lateral cross-sections through the N-well 28. In FIG. 7, the doping density is plotted along the depth of the N-well 28, which shows an initial doping density, which then increases, and then drops off quickly as the junction with the P-type substrate 10 is formed. In FIG. 8, the lateral doping density for one-half of the N-well is shown, wherein a constant doping density drops off underneath the field oxide isolation areas 18. While the N-well portion underneath the isolation area 18 has a fairly consistent doping density, the P-well underneath the field oxide 18 is more lightly doped due to the segregation of boron at the interface between the field oxide 18 and the P-well 10, and due to the much higher thermal diffusivity of boron compared to either phosphorous or arsenic. The P-well underneath the field oxide 18 is thus very lightly doped and is therefore a locus of parasitic leakage paths.
Referring now to FIG. 9, a finished STI integrated circuit includes a P-type substrate 10, an N-well 28, and a P-well 38. Silicon dioxide isolation areas 18 separate the N-well 28 and the P-well 38. Finally, polysilicon 34 completes a typical device, such as an inverter, wherein the gates of the N-channel and P-channel transistors are electrically connected using the polysilicon layer 34 as is known in the art in integrated digital or analog circuits.
The corresponding plan view is shown in FIG. 10. In FIG. 10, the P-well 28 includes a P+-type active area 42, as well as an N+-type N-well tie 40. The polysilicon gate 34 is also shown in FIG. 10. The N-well 38 includes an N+-type active area 44 as well as the polysilicon gate 34. Due to the low doping density underneath the field oxide isolation edge 18, there exists at least one leakage path 46 as shown, extending from the N-well tie 40 to the polysilicon gate 34. As previously explained, the conventional STI processes do not provide sufficient protection against undesirable parasitic leakage paths in an ionizing radiation environment. Additional leakage paths 47 between the source and drain of active area 44 are also shown, occurring near the surface of the integrated circuit under the field oxide 18.
What is desired, therefore, is an STI fabrication method for a radiation hardened semiconductor device capable of functioning in an ionizing radiation environment of approximately 100 krad(Si) or greater.